In the field of semiconductor devices, processing speed has been increasing and power consumption has been decreasing due to a rapid shift to finer design rules. Accordingly, the need for improvement in transistor performance becomes imperative. However, improvement in performance only by the fine design rules will soon hit a ceiling. In this respect, various novel techniques, such as a technique of applying stress to the transistors, have been developed for the improvement in performance.
For example, as shown in FIG. 13, Japanese Unexamined Patent Publication No. 2003-273240 proposes a method for improving the performance of the transistors by covering N-channel MIS transistors 101 with an LP-CVD (Low Pressure Chemical Vapor Deposition) film 103 which applies tensile stress and covering P-channel MIS transistors 102 with a plasma CVD film 104 which applies compressive stress.
However, the above-described method may cause the following problems.
In an SRAM region, the N-channel MIS transistors and the P-channel MIS transistors are densely arranged. Therefore, it is difficult to cover these transistors with different films applying stresses in different directions. If the N-channel and P-channel MIS transistors are covered with a stress applying film of a single kind, the performance of the N-channel MIS transistors and that of the P-channel MIS transistors may greatly vary. More specifically, the stress applying film improves the performance of one of the MIS transistors, but at the same time, it deteriorates the performance of the other MIS transistor.
It may be possible to cover the N-channel MIS transistors and the P-channel MIS transistors with different films applying stresses in different directions. However, when a stress applying insulating film is formed on the entire region and part of it located above any ones of the MIS transistors is removed, parts of sidewalls formed on the side surfaces of the gate electrode are etched away or part of a device isolation region is etched away. As a result, when a shared contact covering from one of the source/drain regions to a gate wiring is formed, junction leakage may increase between the source/drain region and the substrate or short circuit may occur between them.